diff options
| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-06-24 14:45:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 05:59:45 +0000 |
| commit | f8668e98902d0ac6589ca9652206468ab370e2f2 (patch) | |
| tree | d79ccba12bed7394784bd2ba1ce4c81086f4731f /src/soc/intel/tigerlake/romstage/fsp_params.c | |
| parent | 3d6066eaccb641e001ab28a4b46d8f7f0e827f89 (diff) | |
soc/intel/tigerlake: Add CpuReplacementCheck to chip options
Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.
TEST=boot and verified with volteer
Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1a46b7a86d..1f60b52656 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -199,6 +199,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Command Pins Mirrored */ m_cfg->CmdMirror[0] = config->CmdMirror; + + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |