diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-13 13:26:05 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-20 06:22:56 +0000 |
| commit | 82e0a81cf1f999c4d4627ff31c594fd4375c6edc (patch) | |
| tree | 5668f4a2c09efd5d7728beb50b9ba95edbd69680 /src/soc/intel/tigerlake/romstage/fsp_params.c | |
| parent | ab0da17856bc53334f17327e147b941f8cd479af (diff) | |
soc/intel/tigerlake: Merge the recent change from other platforms
Merge the recent change from other platform(ICL/JSL).
- Update SKpMpInit setting
- Update APIs for getting dev info
- Update IGD related setting
- Update debug interface setting
BRANCH=none
TEST=build and boot ripto/volteer
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40349
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 993320054a..6056b4b0c1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -20,8 +20,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t mask = 0; const struct device *dev; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; @@ -60,22 +69,19 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - /* UART Debug Log */ + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : - DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; - m_cfg->PcdIsaSerialUartBase = 0x0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } - /* - * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. - */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) - m_cfg->InternalGfx = 0; - else - m_cfg->InternalGfx = 0x1; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); |