diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-07-05 19:13:15 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-07-09 12:44:26 +0000 |
| commit | 8104effa0dc25bac4693e8d76c1e10039dd47bad (patch) | |
| tree | edc8e60e8acc569b90df57145458801ff670d403 /src/soc/intel/tigerlake/romstage/fsp_params.c | |
| parent | 96dec04207604fdd58ab2f76f8667542c03902e4 (diff) | |
mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
Refer to commit 7736bfc
TEST=Able to build and boot TGLRVP.
Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1f60b52656..662ca06928 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -63,7 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; |