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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 09:57:19 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-10 17:47:03 +0000 |
| commit | a7b60e7dc8788db5de2fe983e9702e167b7f27fe (patch) | |
| tree | 344a8b066b6df40518a6bc15ba3ef5a75df1d924 /src/soc/intel/tigerlake/reset.c | |
| parent | 56fcfb5b4f00830d0c1bf2230e1104045d795c82 (diff) | |
soc/intel/tigerlake: Check TBT & TCSS ports for wake events
Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/reset.c')
0 files changed, 0 insertions, 0 deletions