soc/intel/tgl: Move ME FSR structures to pertinent header

This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.

The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.

The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.

BUG=b:260309647
Test=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

1 files changed, 60 insertions, 26 deletions

diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h
index ed254444b7..fd54de06ac 100644
--- a/src/soc/intel/tigerlake/include/soc/me.h
+++ b/src/soc/intel/tigerlake/include/soc/me.h
@@ -5,39 +5,73 @@
 
 /* ME Host Firmware Status register 1 */
 union me_hfsts1 {
-	u32 data;
+	uint32_t data;
 	struct {
-		u32 working_state: 4;
-		u32 mfg_mode: 1;
-		u32 fpt_bad: 1;
-		u32 operation_state: 3;
-		u32 fw_init_complete: 1;
-		u32 ft_bup_ld_flr: 1;
-		u32 update_in_progress: 1;
-		u32 error_code: 4;
-		u32 operation_mode: 4;
-		u32 reset_count: 4;
-		u32 boot_options_present: 1;
-		u32 invoke_enhance_dbg_mode: 1;
-		u32 bist_test_state: 1;
-		u32 bist_reset_request: 1;
-		u32 current_power_source: 2;
-		u32 reserved: 1;
-		u32 d0i3_support_valid: 1;
+		uint32_t working_state		: 4;
+		uint32_t mfg_mode		: 1;
+		uint32_t fpt_bad		: 1;
+		uint32_t operation_state	: 3;
+		uint32_t fw_init_complete	: 1;
+		uint32_t ft_bup_ld_flr		: 1;
+		uint32_t update_in_progress	: 1;
+		uint32_t error_code		: 4;
+		uint32_t operation_mode		: 4;
+		uint32_t reserved_0		: 4;
+		uint32_t boot_options_present	: 1;
+		uint32_t invoke_enhance_dbg_mode: 1;
+		uint32_t reserved_1		: 5;
+		uint32_t d0i3_support_valid	: 1;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t cpu_replaced		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_replaced_valid	: 1;
+		uint32_t low_power_state	: 1;
+		uint32_t reserved_2		: 22;
 	} __packed fields;
 };
 
 /* ME Host Firmware Status Register 3 */
 union me_hfsts3 {
-	u32 data;
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t fw_sku			: 3;
+		uint32_t reserved_1		: 25;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+	uint32_t data;
 	struct {
-		u32 reserved_0: 4;
-		u32 fw_sku: 3;
-		u32 reserved_7: 2;
-		u32 reserved_9: 2;
-		u32 resered_11: 3;
-		u32 resered_14: 16;
-		u32 reserved_30: 2;
+		uint32_t reserved_0		: 1;
+		uint32_t cpu_debug_disable	: 1;
+		uint32_t reserved_1		: 28;
+		uint32_t fpf_soc_lock		: 1;
+		uint32_t txt_support		: 1;
 	} __packed fields;
 };
 #endif /* _TIGERLAKE_ME_H_ */