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authorBora Guvendik <bora.guvendik@intel.com>2022-08-26 10:55:49 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-08-29 14:25:25 +0000
commit3f6de867e891464c9f5dd22aea2247d5dc86d5e9 (patch)
tree39a0955117f015e5d37eec090e28de32b4692c87 /src/soc/intel/tigerlake/include
parent5502ad1011dfff646120b383e60d233285cf6efa (diff)
soc/intel/alderlake: Rename pcie5 alias
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
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