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authorShaunak Saha <shaunak.saha@intel.com>2020-06-18 23:09:11 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-26 21:45:30 +0000
commit148f8397d2793a465623877d311733eb82e4fe69 (patch)
tree56cd70634daaeeb64affd5931c19aab5adb8bd0c /src/soc/intel/tigerlake/include
parent4276050d13cb8c555f0375d4ec44d33ab5d58402 (diff)
soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch skips CPU side PCIe enablement in FSP if device is disabled in devicetree. Disabling the initialization of CPU PCIe saves ~30ms in FspSiliconInit! BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
-rw-r--r--src/soc/intel/tigerlake/include/soc/pci_devs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index 82d8360524..cfb70cdb9f 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -34,6 +34,9 @@
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+#define SA_DEV_SLOT_CPU_PCIE 0x06
+#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
+
#define SA_DEV_SLOT_TBT 0x07
#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
#define NUM_TBT_FUNCTIONS 4