diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-15 15:55:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:14:11 +0000 |
| commit | d2132469ae86d7287576a2ba3211cdbfeb572703 (patch) | |
| tree | 2f9ccb52774aba1a0e0f9a2d85b59d52a5d1d9c0 /src/soc/intel/tigerlake/include | |
| parent | 425d8640fa3d8e4a43bd9f2cc8f8fd7fedf675c3 (diff) | |
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/cpu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index fb3441db8c..28dfb386c9 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -24,7 +24,4 @@ /* Common Timer Copy (CTC) frequency - 38.4MHz. */ #define CTC_FREQ 38400000 -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif |