From d2132469ae86d7287576a2ba3211cdbfeb572703 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 15 May 2020 15:55:37 +0530 Subject: tigerlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on volteer system Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/include/soc/cpu.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/intel/tigerlake/include') diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index fb3441db8c..28dfb386c9 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -24,7 +24,4 @@ /* Common Timer Copy (CTC) frequency - 38.4MHz. */ #define CTC_FREQ 38400000 -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif -- cgit v1.2.3