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authorElyes Haouas <ehaouas@noos.fr>2024-03-23 15:40:00 +0100
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-03-30 08:29:38 +0000
commitc0d3cf105254c0bbde5c57c8817f5263271fb0fe (patch)
treeb76d060dcb00f6696ded9e39bdc7a7808bcb1e72 /src/soc/intel/tigerlake/fsp_params.c
parent57351dd872746392175f5684b04ac9fb0a5d5538 (diff)
soc/intel: Remove blank lines before '}' and after '{'
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 33269356c8..d5472dd91b 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -563,7 +563,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchFivrExtV1p05RailIccMaximum =
config->ext_fivr_settings.v1p05_icc_max_ma;
-
}
/* Apply minimum assertion width settings if non-zero */