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| author | Shuo Liu <shuo.liu@intel.com> | 2024-09-10 20:07:16 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-09-24 13:40:47 +0000 |
| commit | 0dac2ad3aaa01185ce94fdd0c07e222bbf02b7c0 (patch) | |
| tree | 7cbdce55ff02f86d1d300c2853b0d1d6939fb80f /src/soc/intel/tigerlake/chip.h | |
| parent | ac47ea86752990942a5b887e503e73b35e8140d9 (diff) | |
soc/intel/xeon_sp: Support GNR PCIe root ports
Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.
Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
0 files changed, 0 insertions, 0 deletions