diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2020-03-31 22:56:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-12 20:06:09 +0000 |
| commit | 32b8a51153f7836b841cb2da832e9e78b32e1227 (patch) | |
| tree | ec4783ef165c389ed96a56e96545160890474fc9 /src/soc/intel/tigerlake/chip.h | |
| parent | f318e03495e9a1d43d64516d77a6ae5f2c4d6999 (diff) | |
soc/intel/tigerlake: Control SATA and DMI power optimization
FSP provides the UPD's for SATA and DMI power optimization.
In this patch we are adding the soc's config support to set
those power optimization bits in FSP. By default those
optimizations are enabled. To disable those we need to set
the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1
in devicetree.
BUG=b:151162424
BRANCH=None
TEST=Build and boot volteer and TGL RVP.
Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d9283e1652..e6e106df94 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -288,6 +288,18 @@ struct soc_intel_tigerlake_config { /* HyperThreadingDisable : Yes (1) / No (0) */ uint8_t HyperThreadingDisable; + + /* + * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the DMI Power Optimizer. + */ + uint8_t DmiPwrOptimizeDisable; + + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; }; typedef struct soc_intel_tigerlake_config config_t; |