From 32b8a51153f7836b841cb2da832e9e78b32e1227 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 31 Mar 2020 22:56:13 -0700 Subject: soc/intel/tigerlake: Control SATA and DMI power optimization FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/chip.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/tigerlake/chip.h') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d9283e1652..e6e106df94 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -288,6 +288,18 @@ struct soc_intel_tigerlake_config { /* HyperThreadingDisable : Yes (1) / No (0) */ uint8_t HyperThreadingDisable; + + /* + * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the DMI Power Optimizer. + */ + uint8_t DmiPwrOptimizeDisable; + + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; }; typedef struct soc_intel_tigerlake_config config_t; -- cgit v1.2.3