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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-09 22:53:52 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-02-09 07:53:23 +0000
commitcc93c6e47480de06ce87705a93bc46d806cabbb3 (patch)
tree4fa56de3a3e885246d3892c6897d954bf2e3ffb3 /src/soc/intel/tigerlake/chip.c
parent4949a3dd626560aa504cee18d936d0d7602becfa (diff)
soc/amd,intel: Drop s3_resume parameter on FSP-S functions
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
-rw-r--r--src/soc/intel/tigerlake/chip.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index f07cc58c95..8be04b6624 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -11,7 +11,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -134,7 +133,7 @@ void soc_init_pre_device(void *chip_info)
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();