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authorJeremy Soller <jeremy@system76.com>2021-08-12 10:49:58 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-24 14:49:33 +0000
commitbc071feec18fb7feffbcacde74d101348c65e98e (patch)
tree3000fdc6a32fe37f7dc6b01bc9132cf8b3cdcdc9 /src/soc/intel/tigerlake/chip.c
parent83d795c45b602ed1736e80871b2bd5cd2ccf7490 (diff)
soc/intel/tigerlake: Add TGL-H PEG ports
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
-rw-r--r--src/soc/intel/tigerlake/chip.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 2fd0f0ee7e..dcdaa1ad93 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -73,6 +73,10 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
+ case SA_DEVFN_CPU_PCIE: return "PEG0";
+ case SA_DEVFN_PEG1: return "PEG1";
+ case SA_DEVFN_PEG2: return "PEG2";
+ case SA_DEVFN_PEG3: return "PEG3";
case SA_DEVFN_TCSS_XDCI: return "TXDC";
case SA_DEVFN_TBT0: return "TRP0";
case SA_DEVFN_TBT1: return "TRP1";