From bc071feec18fb7feffbcacde74d101348c65e98e Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 12 Aug 2021 10:49:58 -0600 Subject: soc/intel/tigerlake: Add TGL-H PEG ports Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/tigerlake/chip.c') diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 2fd0f0ee7e..dcdaa1ad93 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -73,6 +73,10 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_CPU_PCIE: return "PEG0"; + case SA_DEVFN_PEG1: return "PEG1"; + case SA_DEVFN_PEG2: return "PEG2"; + case SA_DEVFN_PEG3: return "PEG3"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; -- cgit v1.2.3