diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-02-27 13:08:50 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-01 14:25:38 +0000 |
| commit | fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4 (patch) | |
| tree | 33da5d54d2281c707500049e86cabfff7e4d5077 /src/soc/intel/tigerlake/acpi/tcss.asl | |
| parent | fd51af6286d939a8308ff65260f0fa7ac948507d (diff) | |
soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with
the D3COLD_SUPPORT symbol, as it allows for more granular control.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/tcss.asl')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index be9d306f6e..98337a3e5e 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -676,7 +676,7 @@ Scope (\_SB.PCI0) } } -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -787,7 +787,7 @@ Scope (\_SB.PCI0) STAT = 0 } } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT /* * TCSS xHCI device |