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| author | Subrata Banik <subratabanik@google.com> | 2023-12-13 01:21:31 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-12-18 08:23:39 +0000 |
| commit | 8cf64473cbb3ce0d2bffdd46458fd8a827fd0a9e (patch) | |
| tree | c15d2ced4953d4bc75898f7409e85a07a016df7b /src/soc/intel/tigerlake/acpi/serialio.asl | |
| parent | ed0647a850c973435b382250322d07749c5c4437 (diff) | |
soc/intel/mtl: Adaptively disable 3-strike error for QS silicon
This patch provides a way to mask the 3-strike error on Intel
Meteor Lake SoC platform across pre-prod and prod SoC.
This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types.
Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error.
BUG=b:314883362
TEST=Disable the 3-strike on google/screebo with QS silicon.
Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/serialio.asl')
0 files changed, 0 insertions, 0 deletions