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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-04-30 17:11:02 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-05 22:41:41 +0000 |
| commit | e6e8b3d3371d94d02caf4ff5a9ba4b69b87750c5 (patch) | |
| tree | fbde911ce75fbee1d69f53da89288ef0b35991c5 /src/soc/intel/skylake | |
| parent | cc3637f177c5f1264c43a9aee625bd505e07a92d (diff) | |
soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
Adding GPIO definition for community 3 which is CPU reserved GPIO used
by CPU side PCIe root ports. We did not have this definition since
FSP used to program this GPIOs. Now, instead of FSP, coreboot programs
CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode.
Thus adding definition of this virtual GPIOs in this CL.
BUG=None
BRANCH=None
TEST=Check if correct registers are being programmed
Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions