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authorFurquan Shaikh <furquan@chromium.org>2017-08-25 09:50:15 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-28 01:19:36 +0000
commitc3e4f6344dfec53c0ac5a07632270816a30046b9 (patch)
treefc7272dbbb00b5c184e0fc0e31e1ef98e490e083 /src/soc/intel/skylake
parent5bb27b7815b00ed789f474133eb52c73075a200f (diff)
mainboard/google/poppy: Tune I2C params (hcnt, lcnt, hold time)
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 375 - 400 I2C1: 377 - 400 I2C2: 377 - 400 I2C4: 375 - 397 I2C5: 375 - 397 Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
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