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authorSean Rhodes <sean@starlabs.systems>2021-07-13 13:36:28 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2021-08-03 15:21:04 +0000
commitbc35bed18eba2526bc296cf12e972011bb85613d (patch)
treec2fb86bedeb40dc07bf27b716b00d8fd7147ad81 /src/soc/intel/skylake
parentc0308eb86068970dec906d01094fce43a4b58c16 (diff)
soc/intel/*: Allow configuring 8254 timer via CMOS
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 354a6eed31..39799114ef 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -9,6 +9,7 @@
#include <device/pci_ids.h>
#include <fsp/util.h>
#include <gpio.h>
+#include <option.h>
#include <intelblocks/cfg.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
@@ -28,6 +29,7 @@
#include <soc/systemagent.h>
#include <soc/usb.h>
#include <string.h>
+#include <types.h>
#include "chip.h"
@@ -340,7 +342,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
- params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER);
+ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
+ params->Early8254ClockGatingEnable = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);