diff options
| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-10-12 04:19:42 +0000 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-16 22:03:34 +0000 |
| commit | b53858bacee1b3561ab0c70e3f82196f4e7eb6cb (patch) | |
| tree | 71a05fe3201906f4ef52a81c0848a64ce994dbd2 /src/soc/intel/skylake | |
| parent | 3f1de9add900305730a28be919a21a682ae6b224 (diff) | |
soc/intel/skylake: Rename PcieRpAspm devicetree config
This configuration option shares a name with the FSP UPD, but
is enumerated differently. Change its name to minimise confusion
about the options.
Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4139570f64..549f403384 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -210,8 +210,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; - if (config->PcieRpAspm[i]) - params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + if (config->pcie_rp_aspm[i]) + params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1; if (config->pcie_rp_l1substates[i]) params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 5befb01a91..2584d5d809 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -262,7 +262,7 @@ struct soc_intel_skylake_config { AspmL1, AspmL0sL1, AspmAutoConfig, - } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum { |