diff options
author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-28 15:30:20 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 16:21:29 +0000 |
commit | 6a051f2b49d5d4b9605f4a4a2dfe46cd770704b3 (patch) | |
tree | 64f7f513d57c437e7ad7070014f8971eda4ed63b /src/soc/intel/skylake | |
parent | 57c5af30ddf82585813bfdcb7336d6babe9cb486 (diff) |
soc/intel/skylake: Move UNCORE PRMRR base and mask defines.
UNCORE PRMRR BASE and MASK MSRs are not common, so move to
SOC specific header file and rename the #define to start with MSR_*
Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 2 | ||||
-rw-r--r-- | src/soc/intel/skylake/smmrelocate.c | 4 | ||||
-rw-r--r-- | src/soc/intel/skylake/systemagent.c | 4 |
3 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4ff4ad2d49..0bd7f3ce60 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -32,6 +32,8 @@ #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_VR_MISC_CONFIG2 0x636 diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 482107b111..dbe0c9485b 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -50,8 +50,8 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", relo_params->uncore_emrr_base.lo, relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_PRMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index ba7c3075cd..8af995d133 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -69,9 +69,9 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, uint64_t *prmrr_mask) { msr_t msr; - msr = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); + msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE); *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo; - msr = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR); + msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK); *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; return 0; } |