diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-24 23:57:37 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-17 13:58:15 +0000 |
| commit | 68bacc210945ef7d65dd542765c3be997caf7b4d (patch) | |
| tree | 342aabc7d09a5ac72073f2fb5821ed7729997701 /src/soc/intel/skylake | |
| parent | 6eaffcdbb13b13aad20a4ea0f06f361432daf713 (diff) | |
soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosen
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL, CNL, DNV in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.
For SKL and CNL, this temporarly redundantly disables the PM Timer,
since FSP does that, too. This redundancy is resolved in the follow-up.
Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/pmc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index c2e724f353..b9b85c2e8f 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -101,6 +101,15 @@ void pmc_soc_init(struct device *dev) pci_or_config32(dev, GEN_PMCON_B, 0); setbits32(pwrmbase + GBLRST_CAUSE0, 0); setbits32(pwrmbase + GBLRST_CAUSE1, 0); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pm1_enable_pwrbtn_smi(void *unused) |