summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2015-07-30 10:20:53 -0500
committerAaron Durbin <adurbin@chromium.org>2015-08-14 15:15:28 +0200
commit3b6c398bf4923dfabb486825116783d5208d3035 (patch)
tree0342c299be30f4fec594a8bd055867bc5d424564 /src/soc/intel/skylake
parent85654a66504f2c87f129d3c414995be4b6cdc09f (diff)
skylake: enumerate the SMI status fields
Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/include/soc/pm.h24
-rw-r--r--src/soc/intel/skylake/smihandler.c45
2 files changed, 35 insertions, 34 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 0475e20d78..9409ba2184 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -72,6 +72,30 @@
#define EOS (1 << 1)
#define GBL_SMI_EN (1 << 0)
#define SMI_STS 0x34
+#define SMI_STS_BITS 32
+#define XHCI_SMI_STS_BIT 31
+#define ME_SMI_STS_BIT 30
+#define SERIAL_IO_SMI_STS_BIT 29
+#define ESPI_SMI_STS_BIT 28
+#define GPIO_UNLOCK_SMI_STS_BIT 27
+#define SPI_SMI_STS_BIT 26
+#define SCC_SMI_STS_BIT 25
+#define MONITOR_STS_BIT 21
+#define PCI_EXP_SMI_STS_BIT 20
+#define SMBUS_SMI_STS_BIT 16
+#define SERIRQ_SMI_STS_BIT 15
+#define PERIODIC_STS_BIT 14
+#define TCO_STS_BIT 13
+#define DEVMON_STS_BIT 12
+#define MCSMI_STS_BIT 11
+#define GPIO_STS_BIT 10
+#define GPE0_STS_BIT 9
+#define PM1_STS_BIT 8
+#define SWSMI_TMR_STS_BIT 6
+#define APM_STS_BIT 5
+#define SMI_ON_SLP_EN_STS_BIT 4
+#define LEGACY_USB_STS_BIT 3
+#define BIOS_STS_BIT 2
#define UPWRC 0x3c
#define UPWRC_WS (1 << 8)
#define UPWRC_WE (1 << 1)
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index dddba56ee8..6c959555c2 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -474,39 +474,16 @@ static void southbridge_smi_monitor(void)
typedef void (*smi_handler_t)(void);
-static smi_handler_t southbridge_smi[32] = {
- NULL, /* [0] reserved */
- NULL, /* [1] reserved */
- NULL, /* [2] BIOS_STS */
- NULL, /* [3] LEGACY_USB_STS */
- southbridge_smi_sleep, /* [4] SLP_SMI_STS */
- southbridge_smi_apmc, /* [5] APM_STS */
- NULL, /* [6] SWSMI_TMR_STS */
- NULL, /* [7] reserved */
- southbridge_smi_pm1, /* [8] PM1_STS */
- southbridge_smi_gpe0, /* [9] GPE0_STS */
- southbridge_smi_gpi, /* [10] GPI_STS */
- southbridge_smi_mc, /* [11] MCSMI_STS */
- NULL, /* [12] DEVMON_STS */
- southbridge_smi_tco, /* [13] TCO_STS */
- southbridge_smi_periodic, /* [14] PERIODIC_STS */
- NULL, /* [15] SERIRQ_SMI_STS */
- NULL, /* [16] SMBUS_SMI_STS */
- NULL, /* [17] LEGACY_USB2_STS */
- NULL, /* [18] INTEL_USB2_STS */
- NULL, /* [19] reserved */
- NULL, /* [20] PCI_EXP_SMI_STS */
- southbridge_smi_monitor, /* [21] MONITOR_STS */
- NULL, /* [22] reserved */
- NULL, /* [23] reserved */
- NULL, /* [24] reserved */
- NULL, /* [25] EL_SMI_STS */
- NULL, /* [26] SPI_STS */
- NULL, /* [27] reserved */
- NULL, /* [28] reserved */
- NULL, /* [29] reserved */
- NULL, /* [30] reserved */
- NULL /* [31] reserved */
+static smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+ [SMI_ON_SLP_EN_STS_BIT] = southbridge_smi_sleep,
+ [APM_STS_BIT] = southbridge_smi_apmc,
+ [PM1_STS_BIT] = southbridge_smi_pm1,
+ [GPE0_STS_BIT] = southbridge_smi_gpe0,
+ [GPIO_STS_BIT] = southbridge_smi_gpi,
+ [MCSMI_STS_BIT] = southbridge_smi_mc,
+ [TCO_STS_BIT] = southbridge_smi_tco,
+ [PERIODIC_STS_BIT] = southbridge_smi_periodic,
+ [MONITOR_STS_BIT] = southbridge_smi_monitor,
};
/*
@@ -524,7 +501,7 @@ void southbridge_smi_handler(void)
smi_sts = clear_smi_status();
/* Call SMI sub handler for each of the status bits */
- for (i = 0; i < 31; i++) {
+ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i]) {
southbridge_smi[i]();