diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-08-31 11:20:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-09-11 09:21:13 +0000 |
| commit | 2cc66916e5d5d5b0d2e92e180bae7ac64d30cbac (patch) | |
| tree | 6bd29385190e12d91595e9feec14f7c420b462bb /src/soc/intel/skylake | |
| parent | 910490f3f48d418824276045489d1ceb221e0ba1 (diff) | |
soc/intel/common/block/cse: Move me_read_config32() to common code
me_read_config32() is defined in multiple places, move it to common
location. Also, this function is usually used for reading HFSTS
registers, hence move the HFSTS register definitions to common location.
Also add a funtion to check if the CSE device has been enabled in the
devicetree and it is visible on the bus. This API can be used by
the caller to check before initiating any HECI communication.
TEST=Verified reading HFSTS registers on CML RVP & Hatch board
Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/me.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/me.c | 13 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 5a9acd51f3..fbe5033d7c 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,7 +21,6 @@ /* * Management Engine PCI registers */ -#define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 #define ME_HFS_CWS_REC 2 @@ -169,7 +168,6 @@ union me_hfs2 { } __packed fields; }; -#define PCI_ME_HFSTS3 0x60 #define ME_HFS3_FW_SKU_CONSUMER 0x2 #define ME_HFS3_FW_SKU_CORPORATE 0x3 @@ -186,9 +184,6 @@ union me_hfs3 { } __packed fields; }; -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584f37..9e17ef1e3d 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -26,10 +26,6 @@ #include <stdlib.h> #include <string.h> -static inline u32 me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} /* HFSTS1[3:0] Current Working State Values */ static const char *const me_cws_values[] = { @@ -242,6 +238,9 @@ static void print_me_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; + if (!is_cse_enabled()) + return; + hfs.data = me_read_config32(PCI_ME_HFSTS1); /* * This command can be run only if: @@ -288,6 +287,9 @@ void intel_me_status(void) union me_hfs3 hfs3; union me_hfs6 hfs6; + if (!is_cse_enabled()) + return; + hfs.data = me_read_config32(PCI_ME_HFSTS1); hfs2.data = me_read_config32(PCI_ME_HFSTS2); hfs3.data = me_read_config32(PCI_ME_HFSTS3); @@ -484,6 +486,9 @@ int send_global_reset(void) int status = -1; union me_hfs hfs; + if (!is_cse_enabled()) + goto ret; + /* Check ME operating mode */ hfs.data = me_read_config32(PCI_ME_HFSTS1); if (hfs.fields.operation_mode) |