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| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-05-11 20:27:27 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-05-22 18:11:56 +0200 |
| commit | 2d689f9e0d281b7ebe99340731511b51d9af21cc (patch) | |
| tree | 340ca8198f668139786f92125a2d067c79d284d4 /src/soc/intel/skylake/uart.c | |
| parent | 4bbfe57959e4dcd66528b9c906e3c1b877d1bcbc (diff) | |
soc/intel/common: Add Intel PCIe common code
Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.
Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake/uart.c')
0 files changed, 0 insertions, 0 deletions