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authorHuayang Duan <huayang.duan@mediatek.com>2020-06-24 09:29:25 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-28 09:22:28 +0000
commit27c9fcfc4857907132030b840ad7f21ca8269193 (patch)
treea8b2b983f8d3599e852198fef4eb39c351ce00b9 /src/soc/intel/skylake/uart.c
parent602943f8dac2e6162de8901dd7e6ab98aba42667 (diff)
soc/mediatek/mt8192: Implement dram all channel calibration
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/intel/skylake/uart.c')
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