soc/intel: Add Skylake SOC support

Add the files to support the Skylake SOC.
Matches chromium tree at 927026db

BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform

Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 76 insertions, 62 deletions

diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 47d6385a63..874d95f10a 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
  */
 
 #include <types.h>
@@ -34,6 +35,7 @@
 #include <soc/pci_devs.h>
 #include <soc/smm.h>
 #include <soc/systemagent.h>
+#include "chip.h"
 
 /* This gets filled in and used during relocation. */
 static struct smm_relocation_params smm_reloc_params;
@@ -46,48 +48,44 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
 	wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
 }
 
-static inline void write_emrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
-	wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
-	wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
-}
-
 static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
 {
 	printk(BIOS_DEBUG,
 	       "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
 	       relo_params->uncore_emrr_base.lo,
 	       relo_params->uncore_emrr_mask.lo);
-	wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
-	wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
+	wrmsr(UNCORE_EMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base);
+	wrmsr(UNCORE_EMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask);
 }
 
 static void update_save_state(int cpu,
-                              struct smm_relocation_params *relo_params,
-                              const struct smm_runtime *runtime)
+			      struct smm_relocation_params *relo_params,
+			      const struct smm_runtime *runtime)
 {
 	u32 smbase;
 	u32 iedbase;
 
-	/* The relocated handler runs with all CPUs concurrently. Therefore
+	/*
+	 * The relocated handler runs with all CPUs concurrently. Therefore
 	 * stagger the entry points adjusting SMBASE downwards by save state
-	 * size * CPU num. */
+	 * size * CPU num.
+	 */
 	smbase = relo_params->smram_base - cpu * runtime->save_state_size;
 	iedbase = relo_params->ied_base;
 
 	printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
 	       smbase, iedbase);
 
-	/* All threads need to set IEDBASE and SMBASE to the relocated
+	/*
+	 * All threads need to set IEDBASE and SMBASE to the relocated
 	 * handler region. However, the save state location depends on the
 	 * smm_save_state_in_msrs field in the relocation parameters. If
 	 * smm_save_state_in_msrs is non-zero then the CPUs are relocating
 	 * the SMM handler in parallel, and each CPUs save state area is
 	 * located in their respective MSR space. If smm_save_state_in_msrs
 	 * is zero then the SMM relocation is happening serially so the
-	 * save state is at the same default location for all CPUs. */
+	 * save state is at the same default location for all CPUs.
+	 */
 	if (relo_params->smm_save_state_in_msrs) {
 		msr_t smbase_msr;
 		msr_t iedbase_msr;
@@ -95,8 +93,10 @@ static void update_save_state(int cpu,
 		smbase_msr.lo = smbase;
 		smbase_msr.hi = 0;
 
-		/* According the BWG the IEDBASE MSR is in bits 63:32. It's
-		 * not clear why it differs from the SMBASE MSR. */
+		/*
+		 * According the BWG the IEDBASE MSR is in bits 63:32. It's
+		 * not clear why it differs from the SMBASE MSR.
+		 */
 		iedbase_msr.lo = 0;
 		iedbase_msr.hi = iedbase;
 
@@ -131,9 +131,11 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
 	return relo_params->smm_save_state_in_msrs;
 }
 
-/* The relocation work is actually performed in SMM context, but the code
+/*
+ * The relocation work is actually performed in SMM context, but the code
  * resides in the ramstage module. This occurs by trampolining from the default
- * SMRAM entry point to here. */
+ * SMRAM entry point to here.
+ */
 static void asmlinkage cpu_smm_do_relocation(void *arg)
 {
 	msr_t mtrr_cap;
@@ -155,16 +157,20 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
 
 	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
 
-	/* Determine if the processor supports saving state in MSRs. If so,
+	/*
+	 * Determine if the processor supports saving state in MSRs. If so,
 	 * enable it before the non-BSPs run so that SMM relocation can occur
-	 * in parallel in the non-BSP CPUs. */
+	 * in parallel in the non-BSP CPUs.
+	 */
 	if (cpu == 0) {
-		/* If smm_save_state_in_msrs is 1 then that means this is the
+		/*
+		 * If smm_save_state_in_msrs is 1 then that means this is the
 		 * 2nd time through the relocation handler for the BSP.
 		 * Parallel SMM handler relocation is taking place. However,
 		 * it is desired to access other CPUs save state in the real
 		 * SMM handler. Therefore, disable the SMM save state in MSRs
-		 * feature. */
+		 * feature.
+		 */
 		if (relo_params->smm_save_state_in_msrs) {
 			msr_t smm_feature_control;
 
@@ -172,10 +178,12 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
 			smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;
 			wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
 		} else if (bsp_setup_msr_save_state(relo_params))
-			/* Just return from relocation handler if MSR save
+			/*
+			 * Just return from relocation handler if MSR save
 			 * state is enabled. In that case the BSP will come
 			 * back into the relocation handler to setup the new
-			 * SMBASE as well disabling SMM save state in MSRs. */
+			 * SMBASE as well disabling SMM save state in MSRs.
+			 */
 			return;
 	}
 
@@ -186,14 +194,6 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
 	mtrr_cap = rdmsr(MTRRcap_MSR);
 	if (mtrr_cap.lo & SMRR_SUPPORTED)
 		write_smrr(relo_params);
-
-	if (mtrr_cap.lo & EMRR_SUPPORTED) {
-		write_emrr(relo_params);
-		/* UNCORE_EMRR msrs are package level. Therefore, only
-		 * configure these MSRs on the BSP. */
-		if (cpu == 0)
-			write_uncore_emrr(relo_params);
-	}
 }
 
 static u32 northbridge_get_base_reg(device_t dev, int reg)
@@ -207,7 +207,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
 }
 
 static void fill_in_relocation_params(device_t dev,
-                                      struct smm_relocation_params *params)
+				      struct smm_relocation_params *params)
 {
 	u32 tseg_size;
 	u32 tsegmb;
@@ -217,23 +217,26 @@ static void fill_in_relocation_params(device_t dev,
 	int phys_bits;
 	/* All range registers are aligned to 4KiB */
 	const u32 rmask = ~((1 << 12) - 1);
+	config_t *conf = dev->chip_info;
 
-	/* Some of the range registers are dependent on the number of physical
-	 * address bits supported. */
+	/*
+	 * Some of the range registers are dependent on the number of physical
+	 * address bits supported.
+	 */
 	phys_bits = cpuid_eax(0x80000008) & 0xff;
 
-	/* The range bounded by the TSEGMB and BGSM registers encompasses the
-	 * SMRAM range as well as the IED range. However, the SMRAM available
-	 * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
+	/*
+	 * The range bounded by the TSEGMB and BGSM registers encompasses the
+	 * SMRAM range as well as the IED range.
 	 */
 	tsegmb = northbridge_get_base_reg(dev, TSEG);
 	bgsm = northbridge_get_base_reg(dev, BGSM);
 	tseg_size = bgsm - tsegmb;
 
+	params->ied_size = conf->IedSize;
+	params->smram_size = tseg_size - params->ied_size;
 	params->smram_base = tsegmb;
-	params->smram_size = 4 << 20;
 	params->ied_base = tsegmb + params->smram_size;
-	params->ied_size = tseg_size - params->smram_size;
 
 	/* Adjust available SMM handler memory size. */
 	params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
@@ -248,8 +251,10 @@ static void fill_in_relocation_params(device_t dev,
 	emrr_base = (params->ied_base + (2 << 20)) & rmask;
 	emrr_size = params->ied_size - (2 << 20);
 
-	/* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
-	 * on the number of physical address bits supported. */
+	/*
+	 * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
+	 * on the number of physical address bits supported.
+	 */
 	params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
 	params->emrr_base.hi = 0;
 	params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
@@ -259,7 +264,7 @@ static void fill_in_relocation_params(device_t dev,
 	params->uncore_emrr_base.lo = emrr_base;
 	params->uncore_emrr_base.hi = 0;
 	params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
-	                              MTRRphysMaskValid;
+					MTRRphysMaskValid;
 	params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
 }
 
@@ -280,14 +285,16 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params)
 }
 
 static int install_relocation_handler(int num_cpus,
-                                      struct smm_relocation_params *relo_params)
+				      struct smm_relocation_params *relo_params)
 {
-	/* The default SMM entry can happen in parallel or serially. If the
+	/*
+	 * The default SMM entry can happen in parallel or serially. If the
 	 * default SMM entry is done in parallel the BSP has already setup
 	 * the saving state to each CPU's MSRs. At least one save state size
 	 * is required for the initial SMM entry for the BSP to determine if
 	 * parallel SMM relocation is even feasible.  Set the stack size to
-	 * the save state size, and call into the do_relocation handler. */
+	 * the save state size, and call into the do_relocation handler.
+	 */
 	int save_state_size = sizeof(em64t101_smm_state_save_area_t);
 	struct smm_loader_params smm_params = {
 		.per_cpu_stack_size = save_state_size,
@@ -318,6 +325,9 @@ static void setup_ied_area(struct smm_relocation_params *params)
 
 	ied_base = (void *)params->ied_base;
 
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+
 	/* Place IED header at IEDBASE. */
 	memcpy(ied_base, &ied, sizeof(ied));
 
@@ -326,10 +336,12 @@ static void setup_ied_area(struct smm_relocation_params *params)
 }
 
 static int install_permanent_handler(int num_cpus,
-                                     struct smm_relocation_params *relo_params)
+				     struct smm_relocation_params *relo_params)
 {
-	/* There are num_cpus concurrent stacks and num_cpus concurrent save
-	 * state areas. Lastly, set the stack size to the save state size. */
+	/*
+	 * There are num_cpus concurrent stacks and num_cpus concurrent save
+	 * state areas. Lastly, set the stack size to the save state size.
+	 */
 	int save_state_size = sizeof(em64t101_smm_state_save_area_t);
 	struct smm_loader_params smm_params = {
 		.per_cpu_stack_size = save_state_size,
@@ -341,7 +353,7 @@ static int install_permanent_handler(int num_cpus,
 	printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
 	       relo_params->smram_base);
 	if (smm_load_module((void *)relo_params->smram_base,
-	                     relo_params->smram_size, &smm_params))
+	    relo_params->smram_size, &smm_params))
 		return -1;
 
 	adjust_apic_id_map(&smm_params);
@@ -359,14 +371,15 @@ static int cpu_smm_setup(void)
 
 	fill_in_relocation_params(dev, &smm_reloc_params);
 
-	setup_ied_area(&smm_reloc_params);
+	if (smm_reloc_params.ied_size)
+		setup_ied_area(&smm_reloc_params);
 
 	msr = rdmsr(CORE_THREAD_COUNT_MSR);
 	num_cpus = msr.lo & 0xffff;
 	if (num_cpus > CONFIG_MAX_CPUS) {
 		printk(BIOS_CRIT,
-		       "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
-		       num_cpus, CONFIG_MAX_CPUS);
+			"Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
+			num_cpus, CONFIG_MAX_CPUS);
 	}
 
 	if (install_relocation_handler(num_cpus, &smm_reloc_params)) {
@@ -380,7 +393,6 @@ static int cpu_smm_setup(void)
 	}
 
 	/* Ensure the SMM handlers hit DRAM before performing first SMI. */
-	/* TODO(adurbin): Is this really needed? */
 	wbinvd();
 
 	return 0;
@@ -398,9 +410,8 @@ int smm_initialize(void)
 	/* Run the relocation handler. */
 	smm_initiate_relocation();
 
-	if (smm_reloc_params.smm_save_state_in_msrs) {
+	if (smm_reloc_params.smm_save_state_in_msrs)
 		printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
-	}
 
 	return 0;
 }
@@ -421,16 +432,19 @@ void smm_relocate(void)
 
 void smm_init(void)
 {
-	/* smm_init() is normally called from initialize_cpus() in
+	/*
+	 * smm_init() is normally called from initialize_cpus() in
 	 * lapic_cpu_init.c. However, that path is no longer used. Don't reuse
 	 * the function name because that would cause confusion.
 	 * The smm_initialize() function above is used to setup SMM at the
-	 * appropriate time. */
+	 * appropriate time.
+	 */
 }
 
 void smm_lock(void)
 {
-	/* LOCK the SMM memory window and enable normal SMM.
+	/*
+	 * LOCK the SMM memory window and enable normal SMM.
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */