soc/intel/skylake: Use intel/common/block/smbus code

Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 0 insertions, 110 deletions

diff --git a/src/soc/intel/skylake/smbus.c b/src/soc/intel/skylake/smbus.c
deleted file mode 100644
index dc6c435324..0000000000
--- a/src/soc/intel/skylake/smbus.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/path.h>
-#include <device/smbus.h>
-#include <device/smbus_def.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <soc/iomap.h>
-#include <soc/ramstage.h>
-#include <soc/smbus.h>
-
-static void pch_smbus_init(device_t dev)
-{
-	struct resource *res;
-	u16 reg16;
-
-	/* Enable clock gating */
-	reg16 = pci_read_config32(dev, 0x80);
-	reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
-	pci_write_config32(dev, 0x80, reg16);
-
-	/* Set Receive Slave Address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_4);
-	if (res)
-		outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
-}
-
-static int lsmbus_read_byte(device_t dev, u8 address)
-{
-	u16 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
-
-	return do_smbus_read_byte(res->base, device, address);
-}
-
-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
-{
-	u16 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
-	return do_smbus_write_byte(res->base, device, address, data);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte	= lsmbus_read_byte,
-	.write_byte	= lsmbus_write_byte,
-};
-
-static void smbus_read_resources(device_t dev)
-{
-	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_BASE_ADDRESS;
-	res->size = 32;
-	res->limit = res->base + res->size - 1;
-	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
-		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
-	/* Also add MMIO resource */
-	res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
-}
-
-static struct device_operations smbus_ops = {
-	.read_resources		= &smbus_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.scan_bus		= &scan_smbus,
-	.init			= &pch_smbus_init,
-	.ops_smbus_bus		= &lops_smbus_bus,
-	.ops_pci		= &soc_pci_ops,
-};
-
-static const unsigned short pci_device_ids[] = {
-	0x9d23, /* SunRisePoint LP */
-	0xa123, /* SunRisePoint H */
-	0
-};
-
-static const struct pci_driver pch_smbus __pci_driver = {
-	.ops	 = &smbus_ops,
-	.vendor	 = PCI_VENDOR_ID_INTEL,
-	.devices = pci_device_ids,
-};