soc/intel/skylake: Add C entry bootblock support

List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 7 insertions, 100 deletions

diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 6ae81378a4..7a13084bf5 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,13 +1,10 @@
-verstage-y += cpu.c
-verstage-y += i2c.c
-verstage-y += pch.c
+bootblock-y += cpu.c
+bootblock-y += i2c.c
+bootblock-y += pch.c
+bootblock-y += report_platform.c
+bootblock-y += smbus.c
+
 verstage-y += power_state.c
-verstage-y += report_platform.c
-verstage-y += romstage.c
-verstage-y += smbus.c
-verstage-y += spi.c
-verstage-y += systemagent.c
-verstage-y += uart.c
 
 romstage-y += cpu.c
 romstage-y += i2c.c
@@ -18,4 +15,3 @@ romstage-y += romstage.c
 romstage-y += smbus.c
 romstage-y += spi.c
 romstage-y += systemagent.c
-romstage-y += uart.c
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
index 1196c5eb9d..e8c41cbe81 100644
--- a/src/soc/intel/skylake/romstage/pch.c
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -57,8 +57,7 @@ static void pch_enable_lpc(void)
 	pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
 
 	/* IO Decode Enable */
-	lpc_en = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | GAMEH_LPC_EN |
-		COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
+	lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
 	pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
 	pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
 
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index b16e5aa22c..56a5a92255 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -49,24 +49,6 @@ void soc_pre_ram_init(struct romstage_params *params)
 	soc_fill_pei_data(params->pei_data);
 }
 
-/* SOC initialization before the console is enabled. */
-void car_soc_pre_console_init(void)
-{
-	/* System Agent Early Initialization */
-	systemagent_early_init();
-
-	if (IS_ENABLED(CONFIG_UART_DEBUG))
-		pch_uart_init();
-}
-
-void car_soc_post_console_init(void)
-{
-	report_platform_info();
-	set_max_freq();
-	pch_early_init();
-	i2c_early_init();
-}
-
 int get_sw_write_protect_state(void)
 {
 	u8 status;
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
deleted file mode 100644
index dc417e0d7a..0000000000
--- a/src/soc/intel/skylake/romstage/uart.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/uart.h>
-#include <device/pci_def.h>
-#include <stdint.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr.h>
-#include <soc/romstage.h>
-#include <soc/serialio.h>
-#include <gpio.h>
-
-/* UART2 pad configuration. Support RXD and TXD for now. */
-static const struct pad_config uart2_pads[] = {
-/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-};
-
-void pch_uart_init(void)
-{
-	device_t dev = PCH_DEV_UART2;
-	u32 tmp;
-	u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-
-	/* Set configured UART2 base address */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
-
-	/* Enable memory access and bus master */
-	tmp = pci_read_config32(dev, PCI_COMMAND);
-	tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, tmp);
-
-	/* Take UART2 out of reset */
-	tmp = read32(base + SIO_REG_PPR_RESETS);
-	tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
-		SIO_REG_PPR_RESETS_IDMA;
-	write32(base + SIO_REG_PPR_RESETS, tmp);
-
-	/*
-	 * Set M and N divisor inputs and enable clock.
-	 * Main reference frequency to UART is:
-	 *  120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
-	 */
-	tmp = read32(base + SIO_REG_PPR_CLOCK);
-	tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
-		(SIO_REG_PPR_CLOCK_N_DIV << 16) |
-		(SIO_REG_PPR_CLOCK_M_DIV << 1);
-	write32(base + SIO_REG_PPR_CLOCK, tmp);
-
-	/* Put UART2 in byte access mode for 16550 compatibility */
-	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
-		pcr_andthenor32(PID_SERIALIO,
-		R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
-
-	gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}