diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:20:51 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:22 +0200 |
| commit | e0a49147a6e16987bfd267bb76f7cf146ddf03dc (patch) | |
| tree | dc398ce7d03f989f7e7cccd0f696a44514d07c2c /src/soc/intel/skylake/romstage | |
| parent | 1b6196dec95e12ae44b5cfe62073c3dcd3f52686 (diff) | |
soc/intel/skylake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15671
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/power_state.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index 85234b55c9..209beebe0f 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -54,17 +54,16 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static uint32_t prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - uint32_t prev_sleep_state = SLEEP_STATE_S0; + uint32_t prev_sleep_state = ACPI_S0; if (ps->pm1_sts & WAK_STS) { - switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - case SLP_TYP_S3: - prev_sleep_state = SLEEP_STATE_S3; + switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { + case ACPI_S3: + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + prev_sleep_state = ACPI_S3; break; -#endif - case SLP_TYP_S5: - prev_sleep_state = SLEEP_STATE_S5; + case ACPI_S5: + prev_sleep_state = ACPI_S5; break; } /* Clear SLP_TYP. */ @@ -76,7 +75,7 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps) * from a true G3 state. */ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = SLEEP_STATE_S5; + prev_sleep_state = ACPI_S5; } /* @@ -84,7 +83,7 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps) * need to check both deep sleep well and normal suspend well. * Otherwise just check deep sleep well. */ - if (prev_sleep_state == SLEEP_STATE_S3) { + if (prev_sleep_state == ACPI_S3) { /* PWR_FLR represents deep sleep power well loss. */ uint32_t mask = PWR_FLR; @@ -93,7 +92,7 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps) mask |= SUS_PWR_FLR; if (ps->gen_pmcon_b & mask) - prev_sleep_state = SLEEP_STATE_S5; + prev_sleep_state = ACPI_S5; } return prev_sleep_state; @@ -163,8 +162,7 @@ struct chipset_power_state *fill_power_state(void) int vboot_platform_is_resuming(void) { - int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; - return typ == SLP_TYP_S3; + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } /* |