diff options
author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-03-31 18:11:49 +0530 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2017-05-02 18:26:07 +0200 |
commit | 7146445be9618eb47895782912af28fb627c009d (patch) | |
tree | ec95cd0ab17fecd4ce91bb9b6bff459d9459f3f4 /src/soc/intel/skylake/romstage | |
parent | c261c4b426ac806cca732bb30459f0e6e855828a (diff) |
soc/intel/skylake: Clean up code by using common FAST_SPI module
This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19055
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
-rw-r--r-- | src/soc/intel/skylake/romstage/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 8 | ||||
-rw-r--r-- | src/soc/intel/skylake/romstage/spi.c | 43 |
3 files changed, 4 insertions, 48 deletions
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7dfbd35610..b3f3fabefe 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -5,5 +5,4 @@ romstage-y += pmc.c romstage-y += power_state.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c -romstage-y += spi.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fb261c3c8b..cb704fd635 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> -#include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> @@ -30,6 +28,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <elog.h> +#include <intelblocks/fast_spi.h> #include <reset.h> #include <romstage_handoff.h> #include <soc/pci_devs.h> @@ -38,8 +37,9 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> +#include <stddef.h> +#include <stdint.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -58,7 +58,7 @@ int get_sw_write_protect_state(void) u8 status; /* Return unprotected status if status read fails. */ - return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80); + return fast_spi_flash_read_wpsr(&status) ? 0 : !!(status & 0x80); } /* UPD parameters to be initialized before MemoryInit */ diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c deleted file mode 100644 index 41e06a7933..0000000000 --- a/src/soc/intel/skylake/romstage/spi.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/flash_controller.h> -#include <soc/romstage.h> -#include <spi-generic.h> - -/* - * Minimal set of commands to read WPSR from SPI. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - uint8_t rdsr; - int ret = 0; - - spi_flash_init(); - - /* sending NULL for spiflash struct parameter since we are not - * calling HWSEQ read_status() call via Probe. - */ - ret = pch_hwseq_read_status(NULL, &rdsr); - if (ret) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return ret; - } - *sr = rdsr & WPSR_MASK_SRP0_BIT; - - return 0; -} |