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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2022-08-03 01:13:33 -0700 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-24 15:59:40 +0000 |
| commit | b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 (patch) | |
| tree | e6529bc93f3f22bf00a7c049137f31a59e0eccdb /src/soc/intel/skylake/reset.c | |
| parent | 4b8092aebbcf2316a0b34d340f18bf7d4ae02ed5 (diff) | |
soc/intel/meteorlake: Enable GPIO 4 bits pad mode configuration
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits
GPIO pad mode to configure native function 8 to 15.
BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/skylake/reset.c')
0 files changed, 0 insertions, 0 deletions