diff options
author | Subrata Banik <subrata.banik@intel.com> | 2017-12-06 18:14:01 +0530 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2017-12-08 02:43:18 +0000 |
commit | 3c838c73992d0fe920fe9b5dbee912d83b6c2d7f (patch) | |
tree | f97c239afd4a5180279bb2e998631db1461e8b0f /src/soc/intel/skylake/pch.c | |
parent | 578a79d50037ab86db88e90e0c92d6a24d5be019 (diff) |
soc/intel/skylake: Remove pch_enable_dev() from SoC
PCI resources MMIO space/bus master enabling is handled inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.
TEST=lspci from kernel console shows same pci device list
without and without this patch.
Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/pch.c')
-rw-r--r-- | src/soc/intel/skylake/pch.c | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c index 7084fa28a4..451bebb083 100644 --- a/src/soc/intel/skylake/pch.c +++ b/src/soc/intel/skylake/pch.c @@ -16,14 +16,10 @@ */ #include <arch/io.h> -#include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <soc/pch.h> #include <soc/pci_devs.h> -#include <soc/ramstage.h> u8 pch_revision(void) { @@ -34,33 +30,3 @@ u16 pch_type(void) { return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); } - -#if ENV_RAMSTAGE -void pch_enable_dev(device_t dev) -{ - /* FSP should implement routines to disable PCH IPs */ - u32 reg32; - - /* These devices need special enable/disable handling */ - switch (PCI_SLOT(dev->path.pci.devfn)) { - case PCH_DEV_SLOT_PCIE: - return; - } - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - } else { - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } -} - -#endif |