diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-12-16 23:28:36 -0800 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-15 14:30:07 +0000 |
| commit | fbd6869f918803852352878b0c6138f080780503 (patch) | |
| tree | 3a8bcbbce61dd78e6f70d8b57145b3a44627af88 /src/soc/intel/skylake/p2sb.c | |
| parent | 607ee30403629c4a8542be2686bd27dc508b3987 (diff) | |
soc/intel/tigerlake: Update header files
Modify header files to update/include tigerlake:
- IOMAP BARs according to silicon reference code
- Update Serial IO devices according to PCH EDS
- Add board types
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/p2sb.c')
0 files changed, 0 insertions, 0 deletions