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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 10:09:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-03 09:03:42 +0000 |
| commit | 3fca2c79224f402f11f0b5fac0c5b267c342f6de (patch) | |
| tree | a700496b058c4093eaa25ab69885050d4dc969d8 /src/soc/intel/skylake/nhlt/max98927.c | |
| parent | 71505f5f474b8d4f713fec70f6ac12e6db72517d (diff) | |
soc/intel/alderlake: Add PCIe root port wake sources to elog
Log PCIe root port wake events in the elog.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/nhlt/max98927.c')
0 files changed, 0 insertions, 0 deletions