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authorRizwan Qureshi <rizwan.qureshi@intel.com>2016-08-23 14:31:23 +0530
committerMartin Roth <martinroth@google.com>2016-08-31 20:02:07 +0200
commit1222a73205bd3a0faba988411b4aec6ea8de1059 (patch)
treea2257201ba2a5c6b8fe3b3ee1779ac86956d43ed /src/soc/intel/skylake/memmap.c
parent874a8f961ff537bc12cfca3d9937a07fcda2fe6e (diff)
skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/memmap.c')
-rw-r--r--src/soc/intel/skylake/memmap.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6af13714a0..96debfd53f 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -21,7 +21,6 @@
#include <device/pci.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
#include <stdlib.h>