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| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-21 13:17:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-22 15:31:20 +0000 |
| commit | 6eca3b7b81bdc17efd6413d7ba8ab5fe38b069ce (patch) | |
| tree | fc88b391677f78d8f17e9e2de1241e09b17e08c5 /src/soc/intel/skylake/lpc.c | |
| parent | 3d0e10f2300812766e0efee283b2a0825c4b7b8c (diff) | |
mb/siemens/mc_ehl1: Disable GSPI in devicetree
Since this mainboard does not use GSPI at all, disable all GSPI ports.
Change-Id: I60254e9f4047537d86c972151ec9e33552332959
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/intel/skylake/lpc.c')
0 files changed, 0 insertions, 0 deletions