diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-09-17 11:50:39 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:57:53 +0000 |
| commit | f45eb062da5a78425d52732b0a0a988b30457c24 (patch) | |
| tree | bbf55e6866ac925954aee49a2d9b8b2915854de7 /src/soc/intel/skylake/include | |
| parent | b593366e349673cd4ef5b933849f78e6e958d626 (diff) | |
skylake: SPI code cleanup
Move base address into iomap.h. Use PCI symbols instead of SPI specific
symbols. Fix comments.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/spi.h | 7 |
2 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 333906b348..7dea6ae011 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -53,6 +53,8 @@ #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 +#define SPI_BASE_ADDRESS 0xfe010000 + #define GPIO_BASE_SIZE 0x10000 /* diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h index a31c9b2ceb..cf55e9de05 100644 --- a/src/soc/intel/skylake/include/soc/spi.h +++ b/src/soc/intel/skylake/include/soc/spi.h @@ -26,12 +26,7 @@ * should support most common flash chips. */ #define SPIDVID_OFFSET 0x0 -/* Temporay SPI BASE ADDRESS */ -#define TEMP_SPI_BAR 0xFE010000 -/* SPI BASE ADDRESS Register */ -#define B_PCH_SPI_BAR0_MASK 0x0FFF -#define PCH_SPI_BASE_ADDRESS 0x10 -#define SPIBAR_MEMBAR_MASK 0xFFFFF000 + /* Reigsters within the SPIBAR */ #define SPIBAR_SSFC 0xA1 |