intel/skylake: IRQ programming through UPD

Implemented Device IRQ porgramming, PxRC to IRQ mapping,
GPIO IRQ routing, SCI IRQ select through UPD

BUG=NONE
BRANCH=NONE
CQ-DEPEND=CL:*232948
TEST= build and booted sklrvp,kunimitsu with this changes.

Change-Id: Ic98074491fe5251a48ed55b6fb7ef31809c3abf3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 534bd65e5df8654d745c8efe491a332336c9cdc3
Original-Change-Id: I4ea6f3cdb15d371c6023bfd046f3475290f5aa26
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291403
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12146
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 134 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/include/soc/interrupt.h b/src/soc/intel/skylake/include/soc/interrupt.h
new file mode 100644
index 0000000000..9fba82964a
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/interrupt.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _INTERRUPT_H_
+#define _INTERRUPT_H_
+
+/* Number of all PCH devices */
+#define PCH_MAX_DEV_INT_CONFIG 64
+
+/* Number of PxRC register in ITSS */
+#define PCH_PARC 0
+#define PCH_PBRC 1
+#define PCH_PCRC 2
+#define PCH_PDRC 3
+#define PCH_PERC 4
+#define PCH_PFRC 5
+#define PCH_PGRC 6
+#define PCH_PHRC 7
+#define PCH_MAX_IRQ_CONFIG 8
+
+#define DEVICE_INT_CONFIG(dev, func, line, irqno) {\
+	.Device = dev, \
+	.Function = func, \
+	.IntX = line, \
+	.Irq = irqno }
+
+#define no_int 0
+#define int_A 1
+#define int_B 2
+#define int_C 3
+#define int_D 4
+
+#endif /* _INTERRUPT_H_ */
diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h
index 430a13c38b..fda81423a9 100644
--- a/src/soc/intel/skylake/include/soc/irq.h
+++ b/src/soc/intel/skylake/include/soc/irq.h
@@ -19,6 +19,26 @@
 
 #define GPIO_IRQ14 14
 #define GPIO_IRQ15 15
+
+#define PCH_IRQ10 10
+#define PCH_IRQ11 11
+
+#define SCI_IRQ9 9
+#define SCI_IRQ10 10
+#define SCI_IRQ11 11
+#define SCI_IRQ20 20
+#define SCI_IRQ21 21
+#define SCI_IRQ22 22
+#define SCI_IRQ23 23
+
+#define TCO_IRQ9 9
+#define TCO_IRQ10 10
+#define TCO_IRQ11 11
+#define TCO_IRQ20 20
+#define TCO_IRQ21 21
+#define TCO_IRQ22 22
+#define TCO_IRQ23 23
+
 #define LPSS_I2C0_IRQ 16
 #define LPSS_I2C1_IRQ 17
 #define LPSS_I2C2_IRQ 18
@@ -32,4 +52,52 @@
 #define LPSS_UART2_IRQ 32
 #define SDIO_IRQ 22
 
+#define cAVS_INTA_IRQ 16
+#define SMBUS_INTA_IRQ 16
+#define SMBUS_INTB_IRQ 17
+#define GbE_INTA_IRQ 16
+#define GbE_INTC_IRQ 18
+#define TRACE_HUB_INTA_IRQ 16
+#define TRACE_HUB_INTD_IRQ 19
+
+#define eMMC_IRQ 21
+#define SD_IRQ 23
+
+#define PCIE_1_IRQ 16
+#define PCIE_2_IRQ 17
+#define PCIE_3_IRQ 18
+#define PCIE_4_IRQ 19
+#define PCIE_5_IRQ 16
+#define PCIE_6_IRQ 17
+#define PCIE_7_IRQ 18
+#define PCIE_8_IRQ 19
+#define PCIE_9_IRQ 16
+#define PCIE_10_IRQ 17
+#define PCIE_11_IRQ 18
+#define PCIE_12_IRQ 19
+
+#define SATA_IRQ 16
+
+#define HECI_1_IRQ 16
+#define HECI_2_IRQ 17
+#define IDER_IRQ 18
+#define KT_IRQ 19
+#define HECI_3_IRQ 16
+
+#define XHCI_IRQ 16
+#define OTG_IRQ 17
+#define THRMAL_IRQ 18
+#define CIO_INTA_IRQ 16
+#define CIO_INTD_IRQ 19
+#define ISH_IRQ 20
+
+#define PEG_RP_INTA_IRQ 16
+#define PEG_RP_INTB_IRQ 17
+#define PEG_RP_INTC_IRQ 18
+#define PEG_RP_INTD_IRQ 19
+
+#define IGFX_IRQ 16
+#define SA_THERMAL_IRQ 16
+#define SKYCAM_IRQ 16
+#define GMM_IRQ 16
 #endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 240bd4a4e1..62c9820376 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -48,10 +48,14 @@
 #define  SA_DEV_IGD		_SA_DEV(IGD)
 
 /* PCH Devices */
+#define PCH_DEV_SLOT_ISH	0x13
+#define  PCH_DEVFN_ISH		_PCH_DEVFN(ISH, 0)
+
 #define PCH_DEV_SLOT_XHCI	0x14
 #define  PCH_DEVFN_XHCI		_PCH_DEVFN(XHCI, 0)
 #define  PCH_DEVFN_USBOTG	_PCH_DEVFN(XHCI, 1)
 #define  PCH_DEVFN_THERMAL	_PCH_DEVFN(XHCI, 2)
+#define  PCH_DEVFN_CIO	_PCH_DEVFN(XHCI, 3)
 #define  PCH_DEV_XHCI		_PCH_DEV(XHCI, 0)
 #define  PCH_DEV_USBOTG		_PCH_DEV(XHCI, 1)
 #define  PCH_DEV_THERMAL	_PCH_DEV(XHCI, 2)
@@ -97,6 +101,8 @@
 #define  PCH_DEVFN_PCIE4	_PCH_DEVFN(PCIE, 3)
 #define  PCH_DEVFN_PCIE5	_PCH_DEVFN(PCIE, 4)
 #define  PCH_DEVFN_PCIE6	_PCH_DEVFN(PCIE, 5)
+#define  PCH_DEVFN_PCIE7	_PCH_DEVFN(PCIE, 6)
+#define  PCH_DEVFN_PCIE8	_PCH_DEVFN(PCIE, 7)
 #define  PCH_DEV_PCIE1		_PCH_DEV(PCIE, 0)
 #define  PCH_DEV_PCIE2		_PCH_DEV(PCIE, 1)
 #define  PCH_DEV_PCIE3		_PCH_DEV(PCIE, 2)
@@ -104,10 +110,19 @@
 #define  PCH_DEV_PCIE5		_PCH_DEV(PCIE, 4)
 #define  PCH_DEV_PCIE6		_PCH_DEV(PCIE, 5)
 
+#define PCH_DEV_SLOT_PCIE_1	0x1d
+#define  PCH_DEVFN_PCIE9	_PCH_DEVFN(PCIE_1, 0)
+#define  PCH_DEVFN_PCIE10	_PCH_DEVFN(PCIE_1, 1)
+#define  PCH_DEVFN_PCIE11	_PCH_DEVFN(PCIE_1, 2)
+#define  PCH_DEVFN_PCIE12	_PCH_DEVFN(PCIE_1, 3)
+
 #define PCH_DEV_SLOT_STORAGE	0x1e
 #define  PCH_DEVFN_UART0	_PCH_DEVFN(STORAGE, 0)
 #define  PCH_DEVFN_UART1	_PCH_DEVFN(STORAGE, 1)
+#define  PCH_DEVFN_GSPI0	_PCH_DEVFN(STORAGE, 2)
+#define  PCH_DEVFN_GSPI1	_PCH_DEVFN(STORAGE, 3)
 #define  PCH_DEVFN_EMMC		_PCH_DEVFN(STORAGE, 4)
+#define  PCH_DEVFN_SDIO		_PCH_DEVFN(STORAGE, 5)
 #define  PCH_DEVFN_SDCARD	_PCH_DEVFN(STORAGE, 6)
 #define  PCH_DEV_UART0		_PCH_DEV(STORAGE, 0)
 #define  PCH_DEV_UART1		_PCH_DEV(STORAGE, 1)
@@ -121,6 +136,7 @@
 #define  PCH_DEVFN_SMBUS	_PCH_DEVFN(LPC, 4)
 #define  PCH_DEVFN_SPI		_PCH_DEVFN(LPC, 5)
 #define  PCH_DEVFN_GBE		_PCH_DEVFN(LPC, 6)
+#define  PCH_DEVFN_TRACEHUB		_PCH_DEVFN(LPC, 7)
 #define  PCH_DEV_LPC		_PCH_DEV(LPC, 0)
 #define  PCH_DEV_PMC		_PCH_DEV(LPC, 2)
 #define  PCH_DEV_HDA		_PCH_DEV(LPC, 3)