diff options
| author | Shilpa Sreeramalu <shilpa.sreeramalu@intel.com> | 2015-06-22 21:48:39 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-08-29 07:31:49 +0000 |
| commit | a0f515354be6b852eea9e4dfcb99198523e52579 (patch) | |
| tree | b64e9211ea4a3d971be6ea564fc72e956d3b490e /src/soc/intel/skylake/include | |
| parent | 91a192f6d0e5706595e7b2bf4501aec2c8a674f0 (diff) | |
intel/skylake: Add support for DPTF
This patch adds the ASL files with the DPTF related settings and the
thermal devices enabled in the SOC. It also enables the DPTF setting
at the global NVS level.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7
Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293391
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11430
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/nvs.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 2c83c5f019..7fef1901e2 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -56,8 +56,9 @@ typedef struct { u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u32 rpa[12]; /* 0x30 - 0x5f - Root Port Address */ + u8 dpte; /* 0x60 - Enable DPTF */ - u8 unused[160]; + u8 unused[159]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |