diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-08-14 12:10:48 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-08-20 11:14:47 +0000 |
| commit | 9a016236d4d67e0c95245d0e67ab85ba2a242359 (patch) | |
| tree | ed2ae6f20522e9f6676d246ba41e542838c42ac3 /src/soc/intel/skylake/include | |
| parent | 69e826dab2e6d268031e8c76b4a8011f97a05bbd (diff) | |
soc/intel/skylake/vr_config: Add loadline defaults
In addition to zero IccMax specified by mainboard with socketed CPU, allow
a zero LoadLine default.
The SoC code will fill in the default AC/DC LoadLine values are per
datasheets:
* "7th Generation Intel® Processor Families for H Platforms, Vol 1"
Document Number: 335190-003
* "7th Generation Intel® Processor Families for S Platforms and
Intel ®Core™ X-Series Processor Family, Vol 1"
Document Number: 335195-003
The AC/DC LoadLine is CPU and board specific.
TODO: Find out how to get the LoadLine from vendor firmware and find out
how to map those to different CPU LoadLines.
Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34938
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/vr_config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 465e248700..aebbbdff4a 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -68,6 +68,7 @@ struct vr_config { }; #define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) #if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains |