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authorBarnali Sarkar <barnali.sarkar@intel.com>2015-08-19 14:15:32 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-08-29 07:24:30 +0000
commit7a2defb2ddc0e2872f00bfcdc7c383ed89a55097 (patch)
tree3af12fe14b602856850550a5f2315e99c2bee246 /src/soc/intel/skylake/include
parentd92f6127e109e5bb595b6726a9f7adb61eac2d9d (diff)
intel/skylake: Implement HW Sequence based WP status read functionality
Early(romstage) SPI write protected status read(wpsr) functionality was broken causing 2 sec timeout issue.Implementing HW Seq based rd status operation in romstage. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and tested using below command flashrom -p host --wp-enable [this should enable WP on flash chip] Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked) flashrom -p host --wp-disable [this should disable WP on flash chip] Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked) Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488 Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294445 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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