diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-29 16:17:13 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-11-30 16:27:12 +0000 |
| commit | 771d611f9ea6aa9b6dbf0ea0fffa5fb48e059351 (patch) | |
| tree | 2571040f7190ecd741f9d8060620e722b83a4797 /src/soc/intel/skylake/include | |
| parent | 94dc50e81092cc788a861ee17905b58e4dd17242 (diff) | |
soc/intel/skylake: Set low maximum temperature threshold for Thermal Device
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/thermal.h | 24 |
2 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 7e99d9984c..0a573acb38 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -64,6 +64,8 @@ #define HECI1_BASE_ADDRESS 0xfed1a000 +#define THERMAL_BASE_ADDRESS 0xfe600000 + /* CPU Trace reserved memory size */ #define GDXC_MOT_MEMORY_SIZE (96*MiB) #define GDXC_IOT_MEMORY_SIZE (32*MiB) diff --git a/src/soc/intel/skylake/include/soc/thermal.h b/src/soc/intel/skylake/include/soc/thermal.h new file mode 100644 index 0000000000..31c47c6361 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/thermal.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_THERMAL_H_ +#define _SOC_THERMAL_H_ + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void); + +#endif |