diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-24 15:27:21 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-10-26 01:50:45 +0200 |
| commit | 723a84e2920c8ba52257cf4bf445b23ff01d8754 (patch) | |
| tree | 86ea0f936ee6e9e16e878976a4ad511e7971ce99 /src/soc/intel/skylake/include | |
| parent | aedbfc8f0917b332e648fe6c4333567bd8e58b0d (diff) | |
soc/intel/skylake: Use intel common support to write-protect SPI flash
BUG=chrome-os-partner:58896
Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17116
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/spi.h | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h index c930b5818c..a92b78d0c9 100644 --- a/src/soc/intel/skylake/include/soc/spi.h +++ b/src/soc/intel/skylake/include/soc/spi.h @@ -40,16 +40,7 @@ /* STRAP Data Register*/ #define SPIBAR_RESET_DATA 0xF8 -#define SPI_PRR_MAX 5 -#define SPI_PRR_SHIFT 12 -#define SPI_PRR_MASK 0x7fff -#define SPI_PRR_BASE_SHIFT 0 -#define SPI_PRR_LIMIT_SHIFT 16 -#define SPI_PRR_RPE (1 << 15) /* Read Protect */ -#define SPI_PRR_WPE (1 << 31) /* Write Protect */ -#define SPI_PRR(base, limit) \ - (((((limit) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_LIMIT_SHIFT) |\ - ((((base) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_BASE_SHIFT)) +#define SPI_FPR_MAX 5 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ #define SPI_OPTYPE_0 0x01 /* Write, no address */ @@ -131,6 +122,5 @@ #define SPIBAR_BC_WPD (1 << 0) void *get_spi_bar(void); -int spi_flash_protect(u32 start, u32 size); #endif |