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authorFurquan Shaikh <furquan@chromium.org>2016-12-21 10:58:26 -0800
committerFurquan Shaikh <furquan@google.com>2016-12-23 04:54:35 +0100
commit42cfdf5184b3e94805958a3368f2e049c09119ac (patch)
treeed67de96fd6e25054aca74916acd5e36282c4388 /src/soc/intel/skylake/include
parent45e11aa0a573aba1e4d8ae8dcd2cc87a8ca87dab (diff)
soc/intel/skylake: Use the new SPI driver interface
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/flash_controller.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 00500670fe..25e77344e5 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -28,6 +28,7 @@ int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
void *buf);
int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg);
+void spi_flash_init(void);
#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
@@ -134,7 +135,7 @@ static void writel_(u32 b, void *addr)
#define SPI_FDATA_REGS 16
#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t))
-typedef struct pch_spi_regs {
+typedef struct pch_spi_flash_regs {
uint32_t bfpr;
uint16_t hsfs;
uint16_t hsfc;
@@ -164,7 +165,7 @@ typedef struct pch_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) pch_spi_regs;
+} __attribute__((packed)) pch_spi_flash_regs;
enum {
HSFS_FDONE = 0x0001,