skylake: Support common LPSS I2C driver

Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
that are present on the Skylake-LP PCH with a 120 mHz clock.  The
required lpss_i2c_base_address() method is implemented separately for
verstage/romstage and ramstage environments.

This provides methods to convert to and from "struct device" and the
I2C controller bus number for that device.  These are used to provide
support for the "I2C Bus Operations" that are present in the coreboot
devicetree.

To support the I2C controller before ramstage an early init function
is provided to do minimal initializaiton of the PCI device and assign
a temporary base address for use before memory.  The final base
address is assigned during device enumeration and used during ramstage.

Because it is usually not necessary to enable I2C controllers before
ramstage a config register for the devicetree is provided to perform
early initialization of this controller.  In addition the bus speed
can be set in the devicetree and that speed will be applied when the
device is initialized.  If not provided the default speed is set to
I2C_SPEED_FAST.

This was tested with the google/chell mainboard by reading and writing
from the trackpad and codec devices during both verstage and ramstage.

Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15105
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

3 files changed, 33 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index 038fe7da70..feba3027e7 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -29,6 +29,9 @@
 #define UART_DEBUG_BASE_ADDRESS	0xfe034000
 #define UART_DEBUG_BASE_SIZE	0x1000
 
+#define EARLY_I2C_BASE_ADDRESS	0xfe040000
+#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+
 #define MCH_BASE_ADDRESS	0xfed10000
 #define MCH_BASE_SIZE		0x8000
 
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 74fd1c57b6..476e2c6a56 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -17,6 +17,7 @@
 #ifndef _SOC_PCI_DEVS_H_
 #define _SOC_PCI_DEVS_H_
 
+#include <device/pci_def.h>
 #include <rules.h>
 
 #define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
@@ -147,4 +148,32 @@
 #define  PCH_DEV_SPI		_PCH_DEV(LPC, 5)
 #define  PCH_DEV_GBE		_PCH_DEV(LPC, 6)
 
+/* Convert I2C bus number to PCI device and function */
+static inline int i2c_bus_to_devfn(unsigned bus)
+{
+	switch (bus) {
+	case 0: return PCH_DEVFN_I2C0;
+	case 1: return PCH_DEVFN_I2C1;
+	case 2: return PCH_DEVFN_I2C2;
+	case 3: return PCH_DEVFN_I2C3;
+	case 4: return PCH_DEVFN_I2C4;
+	case 5: return PCH_DEVFN_I2C5;
+	}
+	return -1;
+}
+
+/* Convert PCI device and function to I2C bus number */
+static inline int i2c_devfn_to_bus(unsigned devfn)
+{
+	switch (devfn) {
+	case PCH_DEVFN_I2C0: return 0;
+	case PCH_DEVFN_I2C1: return 1;
+	case PCH_DEVFN_I2C2: return 2;
+	case PCH_DEVFN_I2C3: return 3;
+	case PCH_DEVFN_I2C4: return 4;
+	case PCH_DEVFN_I2C5: return 5;
+	}
+	return -1;
+}
+
 #endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 7fab8ce549..56bace15a7 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -19,6 +19,7 @@
 
 #include <fsp/romstage.h>
 
+void i2c_early_init(void);
 void systemagent_early_init(void);
 void pch_early_init(void);
 void pch_uart_init(void);