soc/intel/skylake: Remove pch_enable_dev() from SoC

PCI resources MMIO space/bus master enabling is handled inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.

TEST=lspci from kernel console shows same pci device list
without and without this patch.

Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 0 insertions, 2 deletions

diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index d7e2fe3546..1dba445a20 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -26,7 +26,6 @@
 #define FSP_MEM_UPD MEMORY_INIT_UPD
 
 void soc_irq_settings(FSP_SIL_UPD *params);
-void pch_enable_dev(device_t dev);
 void soc_init_pre_device(void *chip_info);
 void soc_fsp_load(void);
 const char *soc_acpi_name(const struct device *dev);
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index 065b6c221f..69439149b3 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -27,7 +27,6 @@
 #define FSP_MEM_UPD FSP_M_CONFIG
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
-void pch_enable_dev(device_t dev);
 void soc_fsp_load(void);
 void soc_init_pre_device(void *chip_info);
 void soc_irq_settings(FSP_SIL_UPD *params);