diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-05 12:37:00 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 16:39:28 +0200 |
| commit | 2ee54db24603f51738cbebd6d80c120f2b4db76d (patch) | |
| tree | 32670a0d223cde958305c1b2288b0f09a9e5a3b0 /src/soc/intel/skylake/include | |
| parent | fc4c7d8320d329d3712cb74e527dca4178f71bf8 (diff) | |
soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
This patch to make common PCI device name between APL and SKL.
Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 10d480664d..469d7e9992 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_PCI_DEVS_H_ -#define _SOC_PCI_DEVS_H_ +#ifndef _SOC_SKYLAKE_PCI_DEVS_H_ +#define _SOC_SKYLAKE_PCI_DEVS_H_ #include <device/pci_def.h> #include <rules.h> @@ -23,7 +23,7 @@ #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) @@ -72,17 +72,17 @@ #define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) #define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) -#define PCH_DEV_SLOT_ME 0x16 -#define PCH_DEVFN_ME _PCH_DEVFN(ME, 0) -#define PCH_DEVFN_ME_2 _PCH_DEVFN(ME, 1) -#define PCH_DEVFN_ME_IDER _PCH_DEVFN(ME, 2) -#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3) -#define PCH_DEVFN_ME_3 _PCH_DEVFN(ME, 4) -#define PCH_DEV_ME _PCH_DEV(ME, 0) -#define PCH_DEV_ME_2 _PCH_DEV(ME, 1) -#define PCH_DEV_ME_IDER _PCH_DEV(ME, 2) -#define PCH_DEV_ME_KT _PCH_DEV(ME, 3) -#define PCH_DEV_ME_3 _PCH_DEV(ME, 4) +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) #define PCH_DEV_SLOT_SATA 0x17 #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) |